This invention relates generally to extraction devices that recover a clocking signal from an encoded data signal.
Serial communications is an extremely popular technique for transmitting data from one point to another. Typically, serial data is transmitted either as an asynchronous bit-stream or it may be accompanied by a separate clocking signal that defines the temporal location of each data bit in the stream. This latter type of transmission is known as synchronous serial data.
As serial data rates are increased, use of asynchronous data transmission becomes problematic because recovery of the data bits in the stream cannot be performed reliably. This is because the sampling clock is not synchronous with the transmitting clock. For this reason, use of synchronous data transmission is more appropriate at higher data rates. One drawback associated with the use of synchronous transmission is the fact that a separate clocking signal must be provided alongside the data stream.
Other techniques for transmitting serial data in a synchronous manner incorporate clocking information into the serial data stream. Such synchronous coding schemes guarantee a minimum number of the data state transitions within a given period of time. Furthermore, such encoding techniques guarantee that state transitions within the encoded data stream will be synchronous with a clocking mechanism that created the data stream. Manchester encoding and 4-of-5 encoding are two examples of such encoding techniques that incorporate clocking information in the data bit stream.
Most high-speed network protocols are based on such encoding techniques. This allows a single medium to carry high-speed data and clocking information. The clocking information is inherent in the encoding scheme. In a typical network structure, a media access controller (MAC) comprises a data and clock extraction mechanism. The data and clock extraction mechanism may typically comprise a local oscillator. The local oscillator may be synchronized to the state transitions exhibited by an incoming data bit stream.
Synchronization of the local oscillator may typically be accomplished by comparing the phase of the local oscillator clock to the phase of the state transitions exhibited by the incoming bit-stream. In many cases, the difference in phase between the incoming bit stream and the local oscillator may be used to adjust the frequency of the local oscillator in a continuous feedback structure. The feedback structure is aimed at driving the difference between the phases to negligible levels. This type of a structure is commonly referred to as a phase-locked-loop (PLL).
A typical PLL structure comprises an element called a phase detector. The phase detector receives an encoded bit stream along with a local clock signal.
The local clock may typically be generated by a voltage-controlled-oscillator (VCO) that further comprises the PLL structure. In most PLL structures, the phase detector generates pulses that indicate if the phase of the VCO generated local clock leads or lags the phase of the incoming bit stream transitions. Typically, these pulses are referred to as xe2x80x9cupxe2x80x9d pulses and xe2x80x9cdownxe2x80x9d pulses. A typical PLL structure may further comprise a digital-to-analog (D/A) converter. In some cases, the D/A converter may be a charge-pump converter. This type of converter typically generates a voltage that is proportional to the ratio of the widths of the up and down pulses received from the phase detector.
In some PLL implementations, the phase detector typically generates a down pulse that is of a constant duration, i.e. width. Typically, the pulse width of the down pulse is maintained at xc2xd of a cycle of the local clock. In order to vary the voltage generated by the charge-pump, a typical phase detector may vary the width of the up pulses between zero and one cycle of the local clock. The width of one cycle of the local clock is typically referred to as a xe2x80x9cunit-intervalxe2x80x9d (UI). Hence, the down pulse is typically maintained at 0.5UI and the up pulses may vary between 0 and 1UI.
One disadvantage in varying the pulse width of the up pulse from 0UI to 1UI is that as the PLL begins to converge, the width of the up pulse may be driven to zero. As the width of the up pulse diminishes, a charge-pump D/A converter will experience difficulty in distinguishing the actual width of the up pulse. This typically manifests in poor linearity in the D/A conversion process. Poor linearity in the D/A conversion results in poor jitter characteristics. This ultimately limits the speed at which data and clock can be extracted from an encoded data bit stream.
The present invention comprises a method for extracting clock and data that may be operated at higher frequencies than known methods. The present method comprises generation of a local sampling clock that may be used to recover data from an incoming encoded bit stream. This local sampling clock is typically developed asynchronously from the incoming encoded bit stream. This method teaches a novel method of comparing the phase of the locally generated sampling clock to the phase of state transitions exhibited by the incoming encoded data stream.
According to this illustrative method, this phase comparison results in the creation of xe2x80x9cupxe2x80x9d and xe2x80x9cdownxe2x80x9d pulses. According to the invention, down pulses may be maintained in width approximately equal to 1.5 unit intervals of the local sampling clock. The up pulses may be allowed to vary in width between 1 UI and 2 UIs. By preventing the width of the up pulse from approaching zero, the linearity of the phase comparison may be greatly enhanced. Hence, the scope of the present invention should not be limited to methods where down pulses are maintained at 1.5 UI and up pulses varied between 1 and 2 UI. Rather, the present invention includes those embodiments where the width of either the down or up pulse is not allowed to approach a small time periods so as to adversely affect the linearity of phase detection and control of the frequency of a local oscillator.
The phase difference may be expressed by the ratio of the width of the down pulses to the width of the up pulses. According to one example method, the frequency of the local sampling clock may be adjusted according to the ratio expressing the phase difference.
In some embodiments of this illustrative method, the step of creating down pulses may be accomplished by sampling the incoming encoded bit stream coincident with the locally generated sampling clock. The sampled value may be inverted and then delayed before it is sampled with the inverse of the locally generated sampling clock. The amount of delay introduced before sampling with the inverse of the locally generated sampling clock should be sufficient to allow for the sampling of this signal after the first incidence of the inverse of the local clock that occurs after the incidence of the local clock used to sample the encoded bit stream. The down pulses may then be created by logically ANDing the sampled encoded bit stream with the sampled delayed inverse of the sampled encoded bit stream.
This illustrative method for extracting clock and data from an encoded bit stream provides for the creation of up pulses by first sampling the incoming encoded bit stream coincident with the local sampling clock. The sampled value may again be sampled with the local sampling clock. This generates a twice-sampled encoded bit stream. The inverse of this twice-sampled encoded bit stream may then be logically ANDed with a delayed version of the encoded bit stream. The amount of delay introduced into the encoded bit stream prior to the logical AND function should be approximately equivalent to the time necessary for the state of the twice-sampled encoded bit stream to stabilize.
The invention further comprises a phase-locked-loop that embodies the method of the present invention. Accordingly, the PLL comprises a phase detector that receives an incoming encoded data stream and a locally generated sampling clock. The phase detector generates up and down pulses characteristic of the method described herein. Hence, the phase detector may generate down pulses that are maintained in width approximately equal to 1.5 UIs of the local sampling clock. Likewise, the phase detector may generate up pulses that are allowed to vary in width between 1 UI and 2 UIs of the local sampling clock. Again, the key characteristic of the up and down pulses is that they not be allowed to diminish in width below a critical value where the linearity of phase comparison is adversely affected.
According to one example embodiment, the PLL may further comprise a digital to analog converter capable of generating a control voltage based on the ratio of the widths of the up and down pulses generated by the phase detector. The PLL may further comprise a voltage-controlled oscillator that generates the local sampling clock at a frequency dictated by the control voltage.
In some embodiments of the present invention, the PLL may further comprise a phase detector that comprises a down pulse generator. In these embodiments, the down pulse generator may comprise a first sampling unit that saves the state of the encoded data signal coincident with the local sampling clock. A delay unit further comprises the down pulse generator and delays the inverse of the state saved by this first sampling. The delay unit delays the inverse of the state saved by the first sampling unit beyond the first incidence of the inverse of the local sampling clock that occurs after the incidence of the local sampling clock used to save the state of the encoded bit stream.
The down pulse generator further comprises a second sampling unit that saves the state of the delayed inverse of the state saved by the first sampling unit. This second sampling unit saves the state of its input coincident with the inverse of the local sampling clock. The down pulse generator further comprises an AND gate that generates a down pulse by logically ANDing the state of the encoded bit stream saved by the first sampling unit with the state of the delayed inverse of the sampled encoded bit stream saved by the second sampling unit.
Some embodiments of the PLL may comprise a phase detector that comprises an up pulse generator. According to these example embodiments, the up pulse may be generated by twice-sampling the state of the encoded data signal coincident with the local clock. A delayed version of the encoded data signal may then be logically ANDed with the inverse of the twice-sampled encoded data signal in order to generate the up pulses.
The state of the encoded data signal may be twice-sampled by a first sampling unit that saves the state of the encoded data signal and a second sampling unit that saves the state saved by the first sampling unit. The first and second sampling units that comprise the up pulse generator sample the state of their inputs coincident with the local sampling clock.
The up pulse generator may further comprise a delay unit that delays the encoded data signal by an amount of time approximately equal to the time necessary for the output of second sampling unit to stabilize. The delayed version of the encoded data signal may then be logically ANDed with the inverse of the twice-sampled encoded data signal by an AND gate that further comprises the up pulse generator. The output of the AND gate comprises a signal that carries the up pulses.
The present invention may further comprise a data and clock extraction unit. The data and clock extraction unit comprises a PLL that embodies the method of the present invention and a data sampling unit that saves the state of an incoming encoded bit stream coincident with the sampling clock generated by the PLL. Each sample of the encoded bit stream yields a single bit of incoming data.
In some embodiments, the data and clock extraction unit may further comprise a data reconstruction unit. The data reconstruction unit may receive a plurality of data bits from the data sampling unit and creates data packets comprising some defined plurality of data bits. In one illustrative embodiment, the data reconstruction unit may comprise a state machine to control acquisition of data bits and a shift register that collects data bits at the direction of the state machine.
In some example embodiments, the state machine may comprise a start detector and a length counter. In these embodiments, the start detector receives a stream of data bits from the data sampling unit and searches for a data packet start indicator in the bit stream. Once the data packet start indicator is recognized, the start detector may assert an acquisition signal. The length counter may de-assert the acquisition signal after a predetermined number of bits are received. In these embodiments, the shift register may store incoming data bits so long as the acquisition signal is active.
In another embodiment of a data and clock extraction unit, the state machine may further comprise an address comparison unit. The address comparison unit typically accepts an address field from the shift register and asserts a data ready signal if the address acquired in the shift register matches one or more predefined addresses.